Analog-based DC offset compensation
US11277144B1 · kind B1 · utility
1Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2020 |
| Grant date | Mar 15, 2022 |
| Priority date | — |
| Expiry date | Jun 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for reducing or removing a direct current (DC) offset voltage from one or more analog signals is disclosed. An analog signal may be received by an integrator. The integrator may integrate the analog signal to determine a DC offset error signal. The apparatus may integrate, invert, and amplify the DC offset error signal to provide an analog correction signal. The analog correction signal may be inverted and subtracted from the analog signal. In some implementations, the apparatus may include multiple, independent circuits to reduce or remove DC offset voltages from differential signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.