Ternary in-memory accelerator
US11281429B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Sep 25, 2019 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Oct 2, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.