Memory device
US11282559B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2021 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Mar 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B51/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.