Non-volatile memory device having a reading circuit operating at low voltage
US11282573B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2020 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Jun 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes a memory array, a reading circuit, a column decoder stage, and a read supply voltage generator. The column decoder stage includes selectable bitlines and selection switches. A read supply voltage generator includes a voltage regulation circuit and a dummy column decoder coupled to an output of the voltage regulation circuit and having electrical characteristics correlated to the selected read path. The voltage regulation circuit is configured to receive a first electrical quantity correlated to a desired voltage value on the selected bitline and a second electrical quantity correlated to a desired current value for the selected bitline and to generate a regulated read supply voltage for the column decoder stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.