Bulk semiconductor structure with a multi-level polycrystalline semiconductor region and method
US11282740B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2020 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Aug 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a bulk semiconductor structure that includes a semiconductor substrate with a multi-level polycrystalline semiconductor region that includes one or more first-level portions (i.e., buried portions) and one or more second-level portions (i.e., non-buried portions). Each first-level portion can be within the semiconductor substrate some distance below the top surface (i.e., buried), can be aligned below a monocrystalline semiconductor region and/or a trench isolation region, and can have a first maximum depth. Each second-level portion can be within the semiconductor substrate at the top surface, can be positioned laterally adjacent to a trench isolation region, and can have a second maximum depth that is less than the first maximum depth. Also disclosed herein are method embodiments for forming the bulk semiconductor structure wherein the first-level and second-level portions of the multi-level polycrystalline semiconductor region are concurrently formed (e.g., using a single module).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.