Partitioned substrates with interconnect bridge
US11282806B2 · kind B2 · utility
1Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2019 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Oct 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16251
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to semiconductor structures and, more particularly, to partitioned substrates with interconnect bridge structures and methods of manufacture. The structure includes: a plurality of substrates; at least one chip bonded and electrically connected to each of the plurality of substrates; and an interconnect bridge that physically connects the plurality of substrates and electrically connects each of the plurality of chips bonded to each of the plurality of substrates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.