PMOS transistor including low thermal-budget gate stack
US11282837B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2019 |
| Grant date | Mar 22, 2022 |
| Priority date | — |
| Expiry date | Nov 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28194
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A p-channel metal-oxide-semiconductor (pMOS) transistor including a gate stack which includes: a silicon oxide comprising dielectric interlayer on a substrate, wherein the dielectric interlayer has a thickness below 1 nm; a high-k dielectric layer having a higher dielectric constant compared to the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting down a high-K bandgap of the high-k dielectric layer with relation to a valence band of the substrate, where the first dipole-forming capping layer has a thickness below 2 nm; at least one work function metal above the high-k dielectric layer. Advantageously, the pMOS transistor includes low negative bias temperature instability (NBTI) and therefore high reliability without the use of a reliability anneal which makes the pMOS transistor suitable for use as back end of line (BEOL) devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.