Multi-threaded processor with thread granularity
US11288072B2 · kind B2 · utility
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17References
17Claims
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Key dates
| Filing date | Aug 3, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Aug 3, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-thread processor has a canonical thread map register which outputs a sequence of thread_id values indicating a current thread for execution. The thread map register is programmable to provide granularity of number of cycles of the canonical sequence assigned to each thread. In one example of the invention, the thread map register has repeating thread identifiers in a sequential or non-sequential manner to overcome memory latency and avoid thread stalls. In another example of the invention, separate interrupt tasks are placed on each thread to reduce interrupt processing latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.