Ceremorphic, Inc.
74Patents
74Active
74Granted
68Portfolio score
Filing activity: Aug 3, 2020 → Aug 26, 2023
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11700001B1 | System and method for nanomagnet based logic device | Performing Operations; Transporting | 5 | Active |
| US12081216B1 | PRNG-based chiplet to chiplet secure communication using counter resynchronization | Electricity | 3 | Active |
| US11822472B2 | Memory management unit for multi-threaded architecture | Physics | 1 | Active |
| US11469770B2 | Architecture for multiplier accumulator using unit elements for multiplication, bias, accumulation, and analog to digital conversion over a shared charge transfer bus | Physics | 1 | Active |
| US11640196B2 | Unit element for performing multiply-accumulate operations | Physics | 1 | Active |
| US11693056B1 | Scan chain for memory with reduced power consumption | Physics | 1 | Active |
| US11800647B1 | System and method for skyrmion based logic device | Electricity | 1 | Active |
| US11307779B2 | System and method for flash and RAM allocation for reduced power consumption in a processor | Emerging Cross-Sectional Technologies | 0 | Active |
| US12106069B2 | Power saving floating point multiplier-accumulator with precision-aware accumulation | Physics | 0 | Active |
| US12014152B2 | Multiplier-accumulator unit element with binary weighted charge transfer capacitors | Electricity | 0 | Active |
| US12106110B2 | Multiple interfaces for multiple threads of a hardware multi-thread microprocessor | Physics | 0 | Active |
| US12081213B1 | System and method for skyrmion based logic device | Electricity | 0 | Active |
| US12211536B1 | System and method for nanomagnet based logic device | Electricity | 0 | Active |
| US12026479B2 | Differential unit element for multiply-accumulate operations on a shared charge transfer bus | Electricity | 0 | Active |
| US12026093B1 | System and method for storing and accessing preprocessed data | Physics | 0 | Active |
| US12032926B2 | Chopper stabilized analog multiplier accumulator with binary weighted charge transfer capacitors | Electricity | 0 | Active |
| US11977936B2 | Differential analog multiplier-accumulator | Physics | 0 | Active |
| US12079593B2 | Power saving floating point Multiplier-Accumulator with a high precision accumulation detection mode | Physics | 0 | Active |
| US12105625B2 | Programmable multi-level data access address generator | Physics | 0 | Active |
| US11983537B1 | Multi-threaded processor with power granularity and thread granularity | Physics | 0 | Active |
| US11720436B1 | System for error detection and correction in a multi-thread processor | Physics | 0 | Active |
| US11689213B2 | Architecture for analog multiplier-accumulator with binary weighted charge transfer capacitors | Electricity | 0 | Active |
| US11847457B1 | System for error detection and correction in a multi-thread processor | Physics | 0 | Active |
| US11288072B2 | Multi-threaded processor with thread granularity | Emerging Cross-Sectional Technologies | 0 | Active |
| US11593573B2 | Chopper stabilized analog multiplier unit element with binary weighted charge transfer capacitors | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.