Non-volatile memory reading circuits and methods for reducing sensing delay periods
US11289134B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Sep 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices, systems, and methods for reducing sensing delays for a non-volatile memory reading circuit may include operations for pre-charging a plurality of bit lines coupling a memory array having multiple bit cells with a sensing amplifier. Upon receiving a read request identifying a given bit cell in the memory array, the addressed bit line is decoupled from a bias voltage. The addressed bit line corresponds to the given bit cell and is selected from the plurality of bit lines. With the decoupling from the bias voltage, the addressed bit lines are coupled to the sensing amplifier. After a sensing circuit delay, data stored in the given bit cell is provided to the sensing amplifier via the addressed bit lines coupled to the sensing amplifier. The data stored in the given bit cell may then be interpreted by the sensing amplifier and a corresponding data output signal is generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.