Integrated circuit with asymmetric arrangements of memory arrays
US11289141B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 18, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Feb 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a first array of memory cells, a second array of memory cells, a first pair of complementary data lines, a second pair of complementary data lines, and a third pair of complementary data lines. The first pair of complementary data lines extend along the first array of memory cells, and are coupled to the first array of memory cells. The second pair of complementary data lines extend along the second array of memory cells, and are coupled to the first pair of complementary data lines. The third pair of complementary data lines extend along the second array of memory cells, and are coupled to the second array of memory cells. A number of rows of memory cells in the first array of memory cells is different from a number of rows of memory cells in the second array of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.