Sensing component encapsulated by an encapsulation layer with a roughness surface having a hollow region
US11289396B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2020 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Sep 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor die including a sensing component, an encapsulant extending along sidewalls of the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant and disposed aside the semiconductor die, a patterned dielectric layer disposed on the encapsulant and exposing the sensing component of the semiconductor die, a conductive pattern disposed on the patterned dielectric layer and extending to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV through an alignment opening of the first patterned dielectric layer. The semiconductor die is in a hollow region of the encapsulant, and a top width of the hollow region is greater than a width of the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.