Level shifter circuits
US11290092B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2021 |
| Grant date | Mar 29, 2022 |
| Priority date | — |
| Expiry date | Feb 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the Aoutput of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.