Coordinated in-module RAS features for synchronous DDR compatible memory
US11294571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2020 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | May 6, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.