Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system
US11294820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2020 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Sep 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.