Reconfigurable reduced instruction set computer processor architecture with fractured cores
US11294851B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2018 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | May 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/57
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for reconfiguring a reduced instruction set computer processor architecture are disclosed. Exemplary implementations may: provide a primary processing core consisting of a RISC processor; provide a node wrapper associated with each of the plurality of secondary cores, the node wrapper comprising access memory associates with each secondary core, and a load/unload matrix associated with each secondary core; operate the architecture in a manner in which, for at least one core, data is read from and written to the at least cache memory in a control-centric mode; the secondary cores are selectively partitioned to operate in a streaming mode wherein data streams out of the corresponding secondary core into the main memory and other ones of the plurality of secondary cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.