Locking execution of cores to licensed programmable devices in a data center
US11294992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2019 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Dec 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example hardware accelerator for a computer system includes a programmable device and further includes kernel logic configured in a first programmable fabric of the programmable device, a shell circuit configured in a second programmable fabric of the programmable device, the shell circuit configured to provide an interface between a computer system and the kernel logic, and an intellectual property (IP) checker circuit in the kernel logic The IP checker circuit is configured to obtain a device identifier (ID) from the first programmable fabric and a signed whitelist, the signed whitelist including a list of device IDs and a signature, verify the signature of the signed whitelist, compare the device ID against the list of device IDs, and selectively assert or deassert an enable of the kernel logic in response to presence or absence, respectively, of the device ID in the list of device IDs and verification of the signature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.