Memory device transmitting and receiving data at high speed and low power
US11295808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2020 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Oct 29, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.