Multi-time programmable non-volatile memory cell
US11295825B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2019 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Feb 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.