Semiconductor device including air gaps and method for fabricating the same
US11296088B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2019 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Jul 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/231
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.