Power decoupling attachment
US11297717B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 27, 2017 |
| Grant date | Apr 5, 2022 |
| Priority date | — |
| Expiry date | Feb 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1305
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention may include a method, and resulting structure, of forming a semiconductor structure. The method may include forming a component hole from a first surface to a second surface of a base layer. The method may include placing an electrical component in the component hole. The electrical component has a conductive structure on both ends of the electrical component. The electrical component is substantially parallel to the first surface. The method may include forming a laminate layer on the first surface of the base layer, the second surface of the base layer, and between the base layer and the electrical component. The method may include creating a pair of via holes, where the pair of holes align with the conductive structures on both ends of the electrical component. The method may include forming a conductive via in the pair of via holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.