Elpis Technologies Inc.
51Patents
51Active
51Granted
50Portfolio score
Filing activity: Feb 27, 2017 → Nov 4, 2020
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10734410B2 | Conductive contacts in semiconductor on insulator substrate | Electricity | 3 | Active |
| US10714341B2 | Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch | Electricity | 2 | Active |
| US10937883B2 | Vertical transport FETs having a gradient threshold voltage | Electricity | 2 | Active |
| US10763343B2 | Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy | Electricity | 1 | Active |
| US10734346B2 | Method of manufacturing chip-on-chip structure comprising sinterted pillars | Electricity | 1 | Active |
| US10727121B2 | Thin film interconnects with large grains | Electricity | 1 | Active |
| US10777647B2 | Fin-type FET with low source or drain contact resistance | Electricity | 1 | Active |
| US10727299B2 | Lateral bipolar junction transistor with abrupt junction and compound buried oxide | Electricity | 1 | Active |
| US10741673B2 | Controlling gate profile by inter-layer dielectric (ILD) nanolaminates | Electricity | 0 | Active |
| US10916471B2 | Dual silicide liner flow for enabling low contact resistance | Electricity | 0 | Active |
| US10804278B2 | High density programmable e-fuse co-integrated with vertical FETs | Electricity | 0 | Active |
| US10916468B2 | Semiconductor device with buried local interconnects | Electricity | 0 | Active |
| US11063129B2 | Self-limiting fin spike removal | Electricity | 0 | Active |
| US10755949B2 | Structures, methods and applications for electrical pulse anneal processes | Electricity | 0 | Active |
| US11297717B2 | Power decoupling attachment | Electricity | 0 | Active |
| US10777433B2 | Gas-controlled bonding platform for edge defect reduction during wafer bonding | Electricity | 0 | Active |
| US10777482B2 | Multipart lid for a semiconductor package with multiple components | Electricity | 0 | Active |
| US10727051B2 | Semiconductor nanowire fabrication | Electricity | 0 | Active |
| US10790199B2 | Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering | Electricity | 0 | Active |
| US10978454B2 | Semiconductor device and method of forming the semiconductor device | Electricity | 0 | Active |
| US12229749B2 | Systems methods and devices for increasing security when using smartcards | Physics | 0 | Active |
| US10741559B2 | Spacer for trench epitaxial structures | Electricity | 0 | Active |
| US10957536B2 | Removal of trilayer resist without damage to underlying structure | Electricity | 0 | Active |
| US10804166B2 | Porous silicon relaxation medium for dislocation free CMOS devices | Electricity | 0 | Active |
| US10804107B2 | Well and punch through stopper formation using conformal doping | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.