Save and restore register
US11300614B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Oct 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/462
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A save and restore (SR) register system is disclosed. Some embodiments include a first memory state element (MSE), a second MSE, and a control circuit. The first MSE is configured to: clock in a first data value during a normal mode and hold the first data value during a first testing mode; and clock in a first test sequence during a second testing mode. The second MSE is configured to: clock in the first data value during the normal mode; and clock in a second test sequence during the first testing mode. The control circuit configured to: restore the second MSE to the first data value based on an output port of the first MSE after the second MSE clocks in the second test sequence; and restore the first MSE based on an output port of the second MSE after the first MSE clocks in the first test sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.