Transistion fault testing of funtionally asynchronous paths in an integrated circuit

US11300615B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Prakash Narayanan · Bengaluru, IN
• Sundarrajan Rangachari · Poonamallee, IN
• Prashanth Saraf · Bengaluru, IN

Key dates

• Filing date: Dec 14, 2018
• Grant date: Apr 12, 2022
• Expiry date: Mar 29, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31708
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.