Transistor gates and method of forming
US11302793B2 · kind B2 · utility
3Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Jul 30, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Jul 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.