Gate resistance reduction through low-resistivity conductive layer

US11302818B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Chung-Chiang Wu · Taichung, TW
• Po-Cheng Chen · Taipei, TW
• Kuo-Chan Huang · Taichung, TW
• Hung-Chin Chung · Pingzhen District, TW
• Hsien-Ming Lee · New Taipei, TW
• Chien-Hao Chen · Sanxing, TW

Key dates

• Filing date: Sep 16, 2019
• Grant date: Apr 12, 2022
• Expiry date: Sep 16, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834

Abstract

A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.