Chien-Hao Chen
152Patents
14h-index
217Co-inventors
89Inventor score
Filing activity: Jan 11, 2002 → Jun 7, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6656764B1 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device | Electricity | 75 | Expired |
| US7259050B2 | Semiconductor device and method of making the same | Electricity | 66 | Expired |
| US7052946B2 | Method for selectively stressing MOSFETs to improve charge carrier mobility | Electricity | 37 | Expired |
| US6624090B1 | Method of forming plasma nitrided gate dielectric layers | Electricity | 29 | Expired |
| US7871915B2 | Method for forming metal gates in a gate last process | Electricity | 29 | Active |
| US7164163B2 | Strained transistor with hybrid-strain inducing layer | Electricity | 26 | Expired |
| US8836049B2 | Semiconductor structure and process thereof | Electricity | 23 | Active |
| US6566205B1 | Method to neutralize fixed charges in high K dielectric | Electricity | 19 | Expired |
| US6767847B1 | Method of forming a silicon nitride-silicon dioxide gate stack | Electricity | 19 | Expired |
| US6759302B1 | Method of generating multiple oxides by plasma nitridation on oxide | Emerging Cross-Sectional Technologies | 19 | Expired |
| US8537140B2 | Illuminated touch sensitive surface module and illuminated device thereof | Physics | 18 | Active |
| US7157350B2 | Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration | Electricity | 17 | Expired |
| US7118974B2 | Method of generating multiple oxides by plasma nitridation on oxide | Emerging Cross-Sectional Technologies | 17 | Expired |
| US7232730B2 | Method of forming a locally strained transistor | Electricity | 15 | Expired |
| US8679962B2 | Integrated circuit metal gate structure and method of fabrication | Electricity | 14 | Active |
| US8796695B2 | Multi-gate field-effect transistor and process thereof | Electricity | 14 | Active |
| US7223647B2 | Method for forming integrated advanced semiconductor device using sacrificial stress layer | Emerging Cross-Sectional Technologies | 14 | Expired |
| US7528028B2 | Super anneal for process induced strain modulation | Electricity | 12 | Active |
| US8383502B2 | Integrated high-K/metal gate in CMOS process flow | Electricity | 11 | Active |
| US7482211B2 | Junction leakage reduction in SiGe process by implantation | Electricity | 10 | Active |
| US8193586B2 | Sealing structure for high-K metal gate | Electricity | 7 | Active |
| US8674433B2 | Semiconductor process | Electricity | 7 | Active |
| US8003507B2 | Method of integrating high-K/metal gate in CMOS process flow | Electricity | 7 | Active |
| US7138317B2 | Method of generating multiple oxides by plasma nitridation on oxide | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6914313B2 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device | Emerging Cross-Sectional Technologies | 6 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.