Multi-mode design and operation for transistor mismatch immunity
US11303285B1 · kind B1 · utility
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Key dates
| Filing date | Jun 7, 2021 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Jun 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0896
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop having a charge pump is described. The charge pump has circuitry to select a mode for each semiconductor chip from a plurality of modes to enhance yield. Nine unique modes are defined from which a selection is made for each chip. The selected mode mitigates effects of device mistracking anomalies for each chip. A method is provided to show how the modes are determined and prioritized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.