Method of fabricating circuit board
US11304310B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2020 |
| Grant date | Apr 12, 2022 |
| Priority date | — |
| Expiry date | Oct 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/175
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines. A ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate to cover the plating lines and partially expose the plating regions. At least one metal layer is electroplated on the exposed plating regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.