System for controlling memory operations in system-on-chips
US11307767B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Oct 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip (SoC) includes a system memory, a memory controller, and a memory management system coupled therebetween. The memory management system is configured to receive, from the memory controller, a first control signal that is indicative of a memory operation associated with the system memory, and output and provide a second control signal to the system memory to control an execution of the memory operation. The second control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation. Thus, the memory management system prevents memory corruption of the system memory when an asynchronous reset event is detected in the SoC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.