Stacked via rivets in chip hotspots
US11308257B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Dec 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure including a plurality of dielectric regions is described. The structure can include a rivet cell. The rivet cell can include a set of stacked vias. The rivet cell can extend through a stress hotspot of the structure. A length of the rivet cell can thread through at least one dielectric region among the plurality of dielectric regions. The rivet cell can be among a number of rivet cells inserted in the stress hotspot. The stress hotspot can be among a plurality of stress hotspots across the structure. A length of the rivet cell can be based on a model of a relationship between the length of the rivet cell and an energy release rate of the structure. The rivet cell can thread through an interface between a first dielectric region and a second dielectric region having different dielectric constants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.