Michael S. Gray
25Patents
7h-index
41Co-inventors
69Inventor score
Filing activity: Apr 12, 1999 → Aug 13, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7484197B2 | Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs | Physics | 199 | Active |
| US7503020B2 | IC layout optimization to improve yield | Physics | 107 | Active |
| US9158885B1 | Reducing color conflicts in triple patterning lithography | Physics | 36 | Active |
| US6013225A | Surface densification of machine components made by powder metallurgy | Chemistry; Metallurgy | 18 | Expired |
| US7062729B2 | Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization | Physics | 9 | Expired |
| US7260790B2 | Integrated circuit yield enhancement using Voronoi diagrams | Physics | 9 | Expired |
| US7761818B2 | Obtaining a feasible integer solution in a hierarchical circuit layout optimization | Physics | 8 | Active |
| US8302062B2 | Methods to obtain a feasible integer solution in a hierarchical circuit layout optimization | Physics | 6 | Active |
| US7895562B2 | Adaptive weighting method for layout optimization with multiple priorities | Physics | 5 | Active |
| US7117456B2 | Circuit area minimization using scaling | Physics | 5 | Expired |
| US7735042B2 | Context aware sub-circuit layout modification | Physics | 4 | Active |
| US8296706B2 | Handling two-dimensional constraints in integrated circuit layout | Physics | 4 | Active |
| US7120887B2 | Cloned and original circuit shape merging | Physics | 4 | Expired |
| US7490308B2 | Method for implementing overlay-based modification of VLSI design layout | Physics | 4 | Active |
| US7865848B2 | Layout optimization using parameterized cells | Physics | 2 | Active |
| US9971861B2 | Selective boundary overlay insertion for hierarchical circuit design | Physics | 2 | Active |
| US7818694B2 | IC layout optimization to improve yield | Physics | 2 | Active |
| US8555229B2 | Parallel solving of layout optimization | Physics | 1 | Active |
| US11308257B1 | Stacked via rivets in chip hotspots | Physics | 1 | Active |
| US10885260B1 | Fin-based fill cell optimization | Physics | 1 | Active |
| US11822867B2 | Hierarchical color decomposition of process layers with shape and orientation requirements | Physics | 0 | Active |
| US12112114B2 | Hierarchical color decomposition of library cells with boundary-aware color selection | Physics | 0 | Active |
| US8448124B2 | Post timing layout modification for performance | Physics | 0 | Active |
| US12138634B2 | Mill liner, coupling tool and method of removal of a mill liner | Performing Operations; Transporting | 0 | Active |
| US11055465B2 | Fill techniques for avoiding Boolean DRC failures during cell placement | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.