Periodic reduced word line bias which increases channel boosting
US11309031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Dec 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and techniques are described for increasing channel boosting of NAND string during programming by applying a periodic low word line bias during programming. In one aspect, a low pass voltage, VpassL, is applied to designated word lines to create periodic low points or dips in the channel boosting level. A normal pass voltage, Vpass, is applied to other unselected word lines. The low points create barriers to the movement of electrons in the channel toward the selected word line, to prevent the electrons from pulling down the voltage at the channel region which is adjacent to the selected word line. VpassL can be applied to designated word lines at the source and/or drain sides of the selected word line. A control circuit can be configured with various parameters for implementing the techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.