Memory device
US11309033B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Dec 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device including: a memory area having a first memory block and a second memory block; and a control logic configured to control the first memory block and the second memory block in a first mode and a second mode, wherein in the first mode only a control operation for the first memory block is executable, and in the second mode control operations for the first memory block and the second memory block are executable, wherein the control logic counts the number of accesses made to the second memory block in the first mode, and stores the number of accesses as scan data in the second memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.