Smart erase verify test to detect slow-erasing blocks of memory cells
US11309041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Oct 1, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and techniques are described for determining if a block of memory cells is slow-erasing during an erase operation for the block. An erase operation performs an additional verify test in a specified erase-verify iteration to check the position of the upper tail of the threshold voltage distribution of the memory cells of a block. If the upper tail is too high, this indicates a slow-erasing block, even if the erase operation is successfully completed within an allowable number of erase-verify iterations. The additional verify test can be initiated using a prefix command which is transmitted with an erase command to the memory chip. Or, it can be initiated by a device parameter on the memory chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.