Fin field-effect transistor and method of forming the same
US11309185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Apr 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a gate trench over a semiconductor fin. The gate trench includes an upper portion surrounded by first gate spacers and a lower portion surrounded by second gate spacers and the first gate spacers. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is disposed over a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate electrode overlaying the metal gate in the lower portion of the gate trench, while keeping sidewalls of the first gate spacers and upper surfaces of the second gate spacer overlaid by a second portion of the gate dielectric layer. The method includes removing the second portion of the gate dielectric layer, while remaining the gate electrode substantially intact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.