Method of manufacturing a semiconductor device having a source/drain contact plug with a recessed portion using a mask pattern layer
US11309218B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Jun 11, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.