High density 3D interconnect configuration
US11309246B2 · kind B2 · utility
6Cited by
17References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2020 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Jul 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.