Patent · US Active

Gain and memory error estimation in a pipeline analog to digital converter

US11309902B2 · kind B2 · utility

0Cited by

7References

20Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Srinivas Kumar Reddy Naru · Markapur, IN
Narasimhan Rajagopal · Bengaluru, IN
Shagun Dusad · Bengaluru, IN
Viswanathan Nagarajan · Bengaluru, IN
Visvesvaraya Pentakota · Bengaluru, IN

Key dates

Filing date	Dec 16, 2019
Grant date	Apr 19, 2022
Priority date	—
Expiry date	Dec 16, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH03M1/164
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.