Chip package and power module
US11310904B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2019 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Mar 27, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/049
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.