Buried via in a circuit board
US11310921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2019 |
| Grant date | Apr 19, 2022 |
| Priority date | — |
| Expiry date | Jul 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/063
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method may include forming a plurality of multilayer cores wherein each multilayer core comprises a sheet of cured dielectric material having a layer of metal on each side of the sheet of cured dielectric material, patterning each layer of metal in the plurality of multilayer cores to form wiring traces in each layer of metal, embedding a solder element in at least one sheet of a plurality of sheets of uncured dielectric material, wherein the solder element having a melting point temperature within a temperature range of a curing temperature of the uncured dielectric material, forming a printed circuit board by alternately stacking the plurality of multilayer cores with the plurality of sheets of uncured dielectric material between each multilayer core, laminating the stack of multilayer cores and sheets of uncured dielectric material to cause curing of the sheets of uncured dielectric material and melting of the solder element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.