Serial lane-to-lane skew reduction
US11314277B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2019 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Jul 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples described herein provide a method for reducing lane-to-lane serial skew in an integrated circuit. In an example using a processor-based system, a maximum clock skew is determined from clock skews of respective lanes of a transmitter of the IC. Each of the clock skews corresponds to a skew of a clock signal of the respective lane relative to a same reference clock signal. A skew match amount is determined for each lane of the lanes of the transmitter. The skew match amount for a respective lane of the lanes is based on the maximum clock skew and the clock skew of the respective lane. Configuration data is generated to configure the transmitter to shift incoming data for each lane of the lanes based on the skew match amount for the respective lane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.