Instructions and logic for vector multiply add with zero skipping
US11314515B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 23, 2019 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Dec 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.