Tablewalk takeover
US11314657B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Jan 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a microprocessor, comprising: a translation lookaside buffer (TLB) configured to indicate that a virtual page address corresponding to a physical page address of a page of memory that a memory access instruction is attempting to access is missing in the TLB; a first micro-op corresponding to a first memory access instruction and configured to initiate a first speculative tablewalk based on a miss in the TLB of a first virtual page address; and a second micro-op corresponding to a second memory access instruction, the second micro-op configured to take over an active first speculative tablewalk of the first micro-op at its current stage of processing based on being older than the first micro-op and further based on having a virtual page address and properties that match the first virtual page address and properties for the first memory access instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.