Inventor · Austin, TX, US

Colin Eddy

75Patents
7h-index
13Co-inventors
65Inventor score

Filing activity: Feb 20, 2008 → Dec 2, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US9811468B2 Set associative cache memory with heterogeneous replacement policy Emerging Cross-Sectional Technologies 37 Active
US9760496B2 Simultaneous invalidation of all address translation cache entries associated with an X86 process context identifier Physics 22 Active
US8782348B2 Microprocessor cache line evict array Physics 20 Active
US8392693B2 Fast REP STOS using grabline operations Physics 13 Active
US9842055B2 Address translation cache that supports simultaneous invalidation of common context entries Physics 12 Active
US9244686B2 Microprocessor that translates conditional load/store instructions into variable number of microinstructions Physics 9 Active
US8533437B2 Guaranteed prefetch instruction Physics 7 Active
US8533438B2 Store-to-load forwarding based on load/store address computation source information comparisons Physics 6 Active
US9501286B2 Microprocessor with ALU integrated into load unit Physics 6 Active
US8234450B2 Efficient data prefetching in the presence of load hits Physics 5 Active
US9652398B2 Cache replacement policy that considers memory access type Physics 5 Active
US8161246B2 Prefetching of next physically sequential cache line after cache line that includes loaded page table entry Physics 5 Active
US8433853B2 Prefetching of next physically sequential cache line after cache line that includes loaded page table entry Physics 4 Active
US7996650B2 Microprocessor that performs speculative tablewalks Physics 3 Active
US7827390B2 Microprocessor with private microcode RAM Physics 3 Active
US9542332B2 System and method for performing hardware prefetch tablewalks having lowest tablewalk priority Physics 3 Active
US11467972B2 L1D to L2 eviction Physics 2 Active
US8489823B2 Efficient data prefetching in the presence of load hits Physics 2 Active
US9910785B2 Cache memory budgeted by ways based on memory access type Emerging Cross-Sectional Technologies 2 Active
US9569363B2 Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry Physics 2 Active
US9898418B2 Processor including single invalidate page instruction Physics 2 Active
US9817764B2 Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type Physics 2 Active
US10387318B2 Prefetching with level of aggressiveness based on effectiveness by memory access type Emerging Cross-Sectional Technologies 2 Active
US10114794B2 Programmable load replay precluding mechanism Physics 2 Active
US8539209B2 Microprocessor that performs a two-pass breakpoint check for a cache line-crossing load/store operation Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.