Semiconductor device performing row hammer refresh operation
US11315620B2 · kind B2 · utility
13Cited by
140References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Mar 19, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.