Parallel port enablement in pseudo-dual-port memory designs
US11315630B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2020 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Jun 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pseudo-dual-port memory (PDPM) is disclosed that includes a first memory array bank and a second memory array bank of a plurality of memory array banks. The PDPM also includes parallel pin control logic circuitry configured to perform operations including taking a clock signal, a memory enable signal for a first port, a memory enable signal for a second port, a parallel pin control signal, and address signals for the first and the second memory array banks as inputs and generating a first internal clock and a second internal clock for performing operations corresponding to the first and the second memory array banks at the first port and the second port. A total number of memory array banks may be up to eight memory array banks and each including either a six-transistors (6-T) SRAM bit-cell or an eight-transistors (8-T) SRAM bit-cell in static random access memory architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.