Patent · US Active

Memory testing techniques

US11315654B2 · kind B2 · utility

0Cited by

3References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Andy Wangkun Chen · Austin, US
Yannis Jallamion-Grive · Mouans-Sartoux, FR
Cyrille Dray · Hillsboro, US
Frank David Frederick · Austin, US

Key dates

Filing date	Oct 3, 2018
Grant date	Apr 26, 2022
Priority date	—
Expiry date	Dec 15, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/0409
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein refer to an integrated circuit having first circuitry and second circuitry. The first circuitry receives first input data and bypasses error correction circuitry to determine whether the first input data has one or more first errors. The second circuitry receives second input data and enables the error correction circuitry to determine whether the second input data has one or more second errors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.