Epitaxial blocking layer for multi-gate devices and fabrication methods thereof
US11315785B2 · kind B2 · utility
1Cited by
12References
20Claims
0Family size
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Key dates
| Filing date | Sep 17, 2019 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Sep 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3065
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.