Wafer singulation process control
US11315832B2 · kind B2 · utility
0Cited by
5References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 23, 2016 |
| Grant date | Apr 26, 2022 |
| Priority date | — |
| Expiry date | Dec 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for monitoring and controlling a substrate singulation process is described. Device edges are imaged and identified for analysis. Discrepancies in device edges are noted and used to modify a singulation process and to monitor the operation of singulation processes for anomalous behavior.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.